1. Field of the Disclosure
The present disclosure generally relates to integrated circuits, and more particularly to integrated circuits with electrostatic discharge protection circuits.
2. Description of the Related Art
An electrostatic discharge (ESD) event is a common phenomenon that can occur during handling of integrated circuit (IC) devices. Typically, an electrostatic charge accumulates for any of a variety of reasons and discharges onto the IC device, and may cause damage to the IC device and/or to components of the IC device. Such damage can occur during fabrication, during assembly, and during subsequent handling. ESD events may also occur during operation of the IC device.
Conventionally, integrated circuits are protected from ESD events either by insulating all pins of the circuit from external exposure or by adding ESD protection circuitry. Unfortunately, it is sometimes undesirable or impractical to insulate the pin from the outside world. Moreover, as IC device fabrication technologies have advanced and IC device miniaturization has become increasingly common and desirable, ESD protection devices and structures increasingly have introduced parasitic impacts on circuit performance.
In cellular phone applications, for example, voltage controlled oscillators (VCOs) are often used to provide mixing signals. While the details of the implementation of the oscillators may differ, the VCO typically includes an inductor in parallel with a fixed capacitor and a variable capacitor to form a parallel resonant oscillator. Often, inductors of the VCOs are circuit board mounted or “off-package,” as opposed to being integrated into the circuit. In one configuration, described in U.S. Pat. No. 6,323,735, bondwire inductors can be used to create the inductive component of the oscillator. Due to the sensitivity of the VCO, introduction of an ESD protection circuit can adversely impact the performance of the oscillator. The parasitic impacts of the ESD protection circuitry can introduce a dominant loss mechanism in the oscillator, such as an inductance or capacitance that dwarfs the typical oscillator components and causes the VCO to fail.
Since the pins are typically exposed and since ESD protection circuitry adversely impacts performance of the VCO, the gates and drains of the amplifier transistors within the VCO can be exposed directly to ESD events and associated transients.
Therefore, there is a need for ESD protection techniques that provide ESD protection for an IC having exposed pins without adversely impacting the performance of the IC.